This invention relates to the design of integrated circuit (IC) chips and, more particularly, to embedding Random Access Memory (RAM) and other macrocells in the core of an IC chip.
Floorplanning is an important tool used in designing IC chips to minimize chip area or maximize circuit speed. For example, a chip designer can use a floorplan editor to provide graphical feedback about the size and placement of modules without showing internal layout details. These editors can provide shaded color displays of routing density that allows designers to re-place and xe2x80x9crip-up-and-reroutexe2x80x9d congested areas of a chip. A more detailed description of floorplanning is described in Neil H. E. Weste, Kamran Eshraghian, xe2x80x9cPrinciples of CMOS VLSI Design: A Systems Perspectivexe2x80x9d (1993), which is incorporated herein by reference in its entirety.
In conventional floorplans, macrocells (e.g., RAM) typically are placed in a perimeter area surrounding a core comprising rows of standard cells. Standard cells typically include a row of n-transistors and a row of p-transistors. The active regions of these transistors are separated by a distance based on IC design-rules. Additionally, standard cells usually have fixed physical heights which are selected to take into account such parameters as power dissipation, propagation delay, noise immunity, and area consumption. TO Standard cells can be coupled to a power/ground ring for powering circuitry in the standard cell. The power/ground ring includes power and ground busses which can traverse the tops and the bottoms of the standard cells. The internal areas of standard cells can be used for routing transistors for specific logic gates. A more detailed description of standard cells is described in Neil H. E. Weste, Kamran Eshraghian, xe2x80x9cPrinciples of CMOS VLSI Design: A Systems Perspectivexe2x80x9d (1993).
Conventional chip floorplans pose several problems for IC designs having a large number of macrocells embedded at a single hierarchical level (i.e., flat design). Macrocells can be much larger than standard cells and therefore should be judiciously placed in the chip floorplan to preserve geometric regularity. Unfortunately, the number of macrocells that can be placed in the perimeter area surrounding the standard cell core is physically limited. This physical limitation may require the macrocells to be placed within the core in an ad hoc manner. The ad hoc placement of macrocells in the core may increase the distance of such macrocells from the power/ground ring. This increased distance may make it difficult to adequately power macrocells near the center of the core. Furthermore, the larger dimensions of the macrocells may dictate the placing and routing of the smaller standard cells in the core, thereby making it difficult for chip designers to optimize the chip floorplan. Because the floorplan/layout process described above is an interactive one, any reduction in IC design complexity is highly desirable.
Accordingly, there is a need for structured techniques for embedding RAMS and other macrocells in the core of an IC chip while providing flexibility in floorplan optimization. Such techniques would greatly simplify the design of IC chips.
The present invention is directed to embedding macrocells in the core of an IC chip. In one embodiment, macrocells are arranged in columns and disposed in a standard cell core of an IC chip. The macrocells may abut each other within the columns or may be separated from each other by standard cells which are disposed to fill gaps between the macrocells within the columns. Power/ground rails are disposed vertically along the sides of the columns. The power/ground rails run the full height of the core and couple to a power/ground ring disposed along the perimeter of the core. The power/ground rails also couple to the macrocells and the standard cells and provide power to those cells. In one embodiment, the columns form right angles with horizontal standard cell rows. The right angles enable the macrocells and the standard cells to couple easily to the vertically disposed power/ground rails.
An advantage of the present invention is that the number of macrocells to be embedded in an IC chip is not physically limited by the size of the perimeter area surrounding the core.
Another advantage of the present invention is increased flexibility in floorplan optimization because the macrocells are easily swapped from column to column.
Another advantage of the present invention is increased circuit speeds because macrocells are disposed proximate to standard cells.
Another advantage of the present invention is improved routing because macrocells may be implemented within a single metal layer, thereby enabling other metal layers to be routed freely over the macrocells.
These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings.